The invention relates generally to integrated circuit (xe2x80x9cchipxe2x80x9d) packages, and deals more particularly with decoupling capacitors and stiffeners for chip carriers.
Typically a chip is mounted on an organic or inorganic substrate to form a chip xe2x80x9cpackagexe2x80x9d or xe2x80x9cmodulexe2x80x9d. The mounting can utilize a well known wirebond or xe2x80x9cflip chipxe2x80x9d technique. In the wire bond technique, wires are bonded to pads on the chip and also to pads on the substrate to make an electrical (and mechanical) connection. In the flip-chip arrangement, the chip includes pads on one face and they are mounted by solder balls directly to matching pads on the substrate. This provides both an electrical (and mechanical) connection. One such flip chip bonding technique was developed by International Business Machines Corporation and is called xe2x80x9cControlled Collapse Chip Connectionxe2x80x9d or xe2x80x9cC4xe2x80x9d for short. Other flip chip bonding techniques are well known in the industry. Typically, the chip package or module (whether formed by wire bond or flip chip) is subsequently mounted on a printed circuit board.
Circuitry within chips is noisy, i.e. there are high frequency transients incident to switching of transistors in the chip. This is especially true for modern day CMOS technology. The problem is compounded because of high density of the circuitry. Also, some CMOS designs operate from a low power supply voltage, so moderate voltage transients in the power or ground plane can temporarily cause an improper digital value. In some cases, the noise from the chip can also affect circuitry on the printed circuit board.
It is well known to provide some type of decoupling capacitor between power and ground. For example, it was known to provide decoupling capacitors in the chip, or discrete decoupling capacitors on the chip carrier and on the printed circuit board. Discrete capacitors have metal leads leading to the capacitive element, and there are conductive traces on the chip carrier (or printed circuit board) between the source of the noise and the metal leads. One problem with discrete capacitors is the series resistance and series inductance between the source of the noise and the actual capacitor caused by the metal leads and conductive traces. It was also known to provide xe2x80x9cburied capacitancexe2x80x9d within the printed circuit board. See for example, U.S. Pat. No. 5,079,069 to Howard et al., U.S. Pat. No. 5,010,641 to Sisler, U.S. Pat. No. 6,343,001 to Japp et al., U.S. Pat. No. 5,161,086 to Howard et al, U.S. Pat. No. 6,524,352 to Adae-Amoakoh et al., U.S. Pat. No. 6,496,356 to Japp et al., U.S. Pat. No. 5,972,053 to Hoffarth et al., U.S. Pat. No. 5,796,587 to Lauffer et al., and U.S. Pat. No. 6,343,001 to Papathomas et al. A xe2x80x9cburied capacitancexe2x80x9d is a layer of metal, a layer of dielectric and a layer of metal formed as part of a multi-layer printed circuit board. One metal layer may be a power plane and the other metal layer a ground plane. Such buried capacitance can be formed as follows. Typically the printed circuit board is formed from xe2x80x9ccoresxe2x80x9d laminated together. A xe2x80x9ccorexe2x80x9d is a layer of copper foil and a dielectric layer laminated together. Before the cores are laminated together to form the printed circuit board, the copper layers are circuitized as needed. Those copper layers intended for signal paths have much of the copper etched away to form the signal conductors. Other copper layers intended for power and ground planes have relatively little copper etched away. To form the buried capacitor, a power plane and a ground plane are situated adjacent to each other, separated only by a single layer of dielectric. U.S. Pat. No. 6,343,001 discloses a parallel capacitive structure with two power planes sharing a common ground plane located between the two power planes and a plated through hole through the common ground plane and adjacent dielectric layers to interconnect the two power planes. U.S. Pat. No. 4,937,649 discloses a capacitor on the surface of an integrated circuit.
Some chip carrier substrates are thin, and require a stiffener. It was known to bond a relatively thick metal layer to the chip carrier substrate to stiffen the chip carrier. It was also known to provide a center cutout in the metal layer to house the chip.
Japanese Published Patent Application JP2000-232260A by Ogawa Koju (NGK Spark Plug Co. LTD) discloses a combined capacitor and stiffener for a chip carier. This capacitor/stiffener comprises an electrode 123/copper plate stiffener 121, an electrode 124 and an intervening dielectric layer 122. Electrode 123 covers one face of the capacitor and also wraps around the sides of the capacitor and the perimeter of the other face of the capacitor. After formation, this capacitor is electrically and mechanically connected to a face of a wiring board main body 110 by conductive resin bodies 143 and 144 and to a wiring layer 102. The capacitor/stiffener has an opening in the middle to accomodate the chip.
An object of the present invention is to provide one or more capacitors for a chip carrier, in a manner which is less complicated and less expensive than the prior art.
Another object of the present invention is to provide a composite capacitor/stiffener for a chip carrier, which is less complicated and less expensive than the prior art.
The present invention resides in a chip package comprising a substrate with a composite capacitor/stiffener on the substrate. In one embodiment of the present invention, the substrate comprises a plurality of dielectric layers and a plurality of metallic layers interlaced with the dielectric layers. One of the metallic layers is on a surface of the substrate. Another dielectric layer is adhered onto the one metallic layer. A metallic plate is adhered onto the other dielectric layer, opposite the one metallic layer. The metallic plate is electrically connected to power or ground by a conductor passing through the other dielectric layer. The one metallic layer is electrically connected to ground or power, respectively, such that the metallic plate, the other dielectric layer and the one metallic layer form a capacitor. The one metallic layer is joined to a respective one of the plurality of dielectric layers in a same manner as another of the plurality of metallic layers is joined to another, respective one of the plurality of dielectric layers.
The invention also resides in a chip package comprising a substrate and another composite capacitor/stiffener. A first metallic plate is on the substrate. The first metallic plate has a cutout to receive the chip and is connected to power or ground. A dielectric layer is on the first metallic plate. A second metallic plate is on the dielectric layer, opposite the first metallic plate. The second metallic plate has a cutout aligned with the cutout of the first metallic plate to receive the chip. The second metallic plate is connected to power or ground to form a capacitor from the first metallic plate, the dielectric layer and the second metallic plate. The second metallic plate is connected to power or ground by a conductor passing through the dielectric layer and the first metallic plate.
The invention also resides in a chip package comprising a substrate and another composite capacitor/stiffener. The substrate includes a power or ground layer on a surface of the substrate. A first dielectric layer is on the power or ground layer of the substrate. A first metallic plate is on the first dielectric layer. The first metallic plate is connected to a power level or ground such that the power or ground layer of the substrate, the first dielectric layer and the first metallic plate form a first capacitor. A second dielectric layer is on the first metallic plate. A second metallic plate is on the second dielectric layer, opposite the first metallic plate. The second metallic plate is connected to a power level or ground such that the second metallic plate, the second dielectric layer and the first metallic plate form a second capacitor. The second metallic plate is connected to the power level or ground by a conductor passing through the second dielectric layer, the first metallic plate and the first dielectric layer. The second metallic plate, the second dielectric layer, the first metallic plate and the first dielectric layer all have a cutout to receive the chip.